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3.3 volt cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 IDT72V3614 1 1 may 2003 ? 2003 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-4663/1 idt and the idt logo are registered trademarks of integrated device technology, inc. syncbififo is a trademark of integrated de vice technology, inc. commercial temperature range features: ? ? ? ? ? two independent clocked fifos (64 x 36 storage capacity each) buffering data in opposite directions ? ? ? ? ? supports clock frequencies up to 83 mhz ? ? ? ? ? fast access times of 8 ns ? ? ? ? ? free-running clka and clkb can be asynchronous or coinci- dent (simultaneous reading and writing of data on a single clock edge is permitted) ? ? ? ? ? mailbox bypass register for each fifo ? ? ? ? ? dynamic port b bus sizing of 36 bits (long word), 18 bits (word), and 9 bits (byte) ? ? ? ? ? selection of big- or little-endian format for word and byte bus sizes ? ? ? ? ? three modes of byte-order swapping on port b ? ? ? ? ? programmable almost-full and almost-empty flags ? ? ? ? ? microprocessor interface control logic ? ? ? ? ? efa , ffa , aea , and afa flags synchronized by clka ? ? ? ? ? efb , ffb , aeb , and afb flags synchronized by clkb ? ? ? ? ? passive parity checking on each port ? ? ? ? ? parity generation can be selected for each port ? ? ? ? ? available in 132-pin plastic quad flat package (pqf), or space saving 120-pin thin quad flat package (tqfp) ? ? ? ? ? pin and functionally compatible version of the 5v operating idt723614 ? ? ? ? ? industrial temperature range (?40 c to +85 c) is available functional block diagram mail 1 register input register output register clka csa w/ r a ena mba port-a control logic device control rst clkb csb w/ r b enb port-b control logic mbf1 4663 drw 01 mail 2 register write pointer read pointer status flag logic parity gen/check a 0 - a 35 36 ram array 64 x 36 parity generation parity gen/check programmable flag offset register status flag logic input register output register ram array 64 x 36 parity generation read pointer pefb pgb efb aeb ffb afb odd/ even ffa afa fs0 fs1 efa aea pga pefa mbf2 write pointer fifo2 fifo1 36 36 be siz0 siz1 sw0 sw1 bus-matching & byte swapping b 0 -b 35 bus-matching & byte swapping
2 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range gnd aeb efb b 0 b 1 b 2 gnd b 3 b 4 b 5 b 6 v cc b 7 b 8 b 9 gnd b 10 b 11 v cc b 12 b 13 b 14 gnd b 15 b 16 b 17 b 18 b 19 b 20 gnd b 21 b 22 b 23 gnd aea efa a 0 a 1 a 2 gnd a 3 a 4 a 5 a 6 v cc a 7 a 8 a 9 gnd a 10 a 11 v cc a 12 a 13 a 14 gnd a 15 a 16 a 17 a 18 a 19 a 20 gnd a 21 a 22 a 23 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 4663 drw 02 117 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 v cc v cc a 24 a 25 a 26 a 27 gnd a 28 a 29 v cc a 30 a 31 a 32 gnd a 33 a 34 a 35 gnd b 35 b 34 b 33 gnd b 32 b 31 b 30 v cc b 29 b 28 b 27 gnd b 26 b 25 b 24 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 afb afa ffa csa ena clka w/ r a v cc pga fs 0 odd/ even fs 1 pefa mbf2 rst be gnd sw1 sw0 siz1 mbf1 gnd pefb v cc w/ r b clkb enb csb ffb gnd mba siz0 pgb description: the IDT72V3614 is a pin and functionally compatible version of the idt723614, designed to run off a 3.3v supply for exceptionally low power consumption. this device is monolithic, high-speed, low-power cmos bidirectional clocked fifo memory. it supports clock frequencies up to 83 mhz and has read access times as fast as 8 ns. the fifo operates in idt standard mode. two independent 64 x 36 dual-port sram fifos on board the chip buffer data in opposite directions. each fifo has flags to indicate empty and full conditions and two programmable flags (almost-full and almost-empty) to pin configurations indicate when a selected number of words is stored in memory. fifo data on port b can be input and output in 36-bit, 18-bit, and 9-bit formats with a choice of big- or little-endian configurations. three modes of byte-order swapping are possible with any bus size selection. communication between each port can bypass the fifos via two 36-bit mailbox registers. each mailbox register has a flag to signal when new mail has been stored. parity is checked passively on each port and may be ignored if not desired. parity generation can be selected for data read from each port. two or more devices can be used in parallel to create wider data paths. notes: 1. nc - no internal connection. 2. uses yamaichi socket ic51-1324-828. * electrical pin 1 in center of beveled edge. pin 1 identifier in corner. pqfp (2) (pq132-1, order code: pqf) top view *
3 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range tqfp (pn120-1, order code: pf) top view pin configurations (continued) description (continued): this device is a clocked fifo, which means each port employs a synchronous interface. all data transfers through a port are gated to the low- to-high transition of a continuous (free-running) port clock by enable signals. the clocks for each port are independent of one another and can be asynchronous or coincident. the enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses con- trolled by a synchronous interface. the full flag ( ffa , ffb ) and almost-full flag ( afa , afb ) of a fifo are two-stage synchronized to the port clock that writes data to its array. the empty flag ( efa , efb ) and almost-empty ( aea , aeb ) flag of a fifo are two stage synchronized to the port clock that reads data from its array. the IDT72V3614 is characterized for operation from 0 c to 70 c. industrial temperature range (?40 c to +85 c) is available by special order. this device is fabricated using idt's high speed, submicron cmos technology. b 22 b 21 gnd b 20 b 19 b 18 b 17 b 16 b 15 b 14 b 13 b 12 b 11 b 10 gnd b 9 b 8 b 7 v cc b 6 b 5 b 4 b 3 gnd b 2 b 1 b 0 efb aeb afb a 23 a 22 a 21 gnd a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 gnd a 9 a 8 a 7 v cc a 6 a 5 a 4 a 3 gnd a 2 a 1 a 0 efa aea 4663 drw 03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 91 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 afa ffa csa ena clka w/ r a v cc pga pefa mbf 2 mba fs 1 fs 0 odd/ even rst gnd be sw1 sw0 siz1 siz0 mbf 1 pefb pgb v cc w/ r b clkb enb csb ffb 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 b 23 a 24 a 25 a 26 v cc a 27 a 28 a 29 gnd a 30 a 31 a 34 a 35 b 35 gnd b 34 b 33 b 32 b 30 b 31 gnd b 29 b 28 b 27 v cc b 26 b 25 b 24 a 32 a 33
4 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range symbol name i/o description a0-a35 port a data i/o 36-bit bidirectional data port for side a. aea port a almost- o programmable almost-empty flag synchronized to clka. it is low when the number of 36-bit words in empty flag (port a) fifo2 is less than or equal to the value in the offset register, x. aeb port b almost- o programmable almost-empty flag synchronized to clkb. it is low when the number of 36-bit words in empty flag (port b) fifo1 is less than or equal to the value in the offset register, x. afa port a almost-full o programmable almost-full flag synchronized to clka. it is low when the number of 36-bit empty flag (port a) locations in fifo1 is less than or equal to the value in the offset register, x. afb port b almost-full o programmable almost-full flag synchronized to clkb. it is low when the number of 36-bit empty flag (port b) locations in fifo2 is less than or equal to the value in the offset register, x. b0-b35 port b data i/o 36-bit bidirectional data port for side b. be big-endian select i selects the bytes on port b used during byte or word data transfer. a low on be selects the most significant bytes on b0-b35 for use, and a high selects the least significant bytes. clka port a clock i clka is a continuous clock that synchronizes all data transfers through port a and can be asynchronous or coincident to clkb. efa , ffa , afa , and aea are synchronized to the low-to-high transition of clka. clkb port b clock i clkb is a continuous clock that synchronizes all data transfers through port b and can be asynchronous or coincident to clka. port b byte swapping and data port sizing operations are also synchronous to the low-to-high transition of clkb. efb , ffb , afb , and aeb are synchronized to the low-to-high transition of clkb. csa port a chip select i csa must be low to enable a low-to-high transition of clka to read or write data on port a. the a0-a35 outputs are in the high-impedance state when csa is high. csb port b chip select i csb must be low to enable a low-to-high transition of clkb to read or write data on port b. the b0-b35 outputs are in the high-impedance state when csb is high. efa port a empty flag o efa is synchronized to the low-to-high transition of clka. when efa islow, fifo2 is empty, and (port a) and reads from its memory are disabled. data can be read from fifo2 to the output register when efa is high. efa is forced low when the device is reset and is set high by the second low-to-high transition of clka after data is loaded into empty fifo2 memory. efb port b empty flag o efb is synchronized to the low-to-high transition of clkb. when efb is low, the fifo1 is empty, and (port b) and reads from its memory are disabled. data can be read from fifo1 to the output register when efb is high. efb is forced low when the device is reset and is set high by the second low-to-high transition of clkb after data is loaded into empty fifo1 memory. ena port a enable i ena must be high to enable a low-to-high transition of clka to read or write data on port a. enb port b enable i enb must be high to enable a low-to-high transition of clkb to read or write data on port b. ffa port a full flag o ffa is synchronized to the low-to-high transition of clka. when ffa is low, fifo1 is full, and writes (port a) to its memory are disabled. ffa is forced low when the device is reset and is set high by the second low-to-high transition of clka after reset. ffb port b full flag o ffb is synchronized to the low-to-high transition of clkb. when ffb is low, fifo2 is full, and writes (port b) writes to its memory are disabled. ffb is forced low when the device is reset and is set high by the second low-to-high transition of clkb after reset. fs1, fs0 flag-offset i the low-to-high transition of rst latches the values of fs0 and fs1, which selects one of four preset selects values for the almost-full flag and almost-empty flag offset. mba port a mailbox i a high level on mba chooses a mailbox register for a port a read or write operation. when the a0-a35 select outputs are active, a high level on mba selects data from the mail2 register for output, and a low level selects fifo2 output register data for output. mbf1 mail1 register o mbf1 is set low by a low-to-high transition of clka that writes data to the mail1 register. writes to the flag mail1 register are inhibited while mbf1 is set low. mbf1 is set high by a low-to-high transition of clkb when a port b read is selected and both siz1 and siz0 are high. mbf1 is set high when the device is reset. pin description
5 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range pin description (continued) symbol name i/o description mbf2 mail2 register o mbf2 is set low by a low-to-high transition of clkb that writes data to the mail2 register. writes to the flag mail2 register are inhibited while mbf2 is set low. mbf2 is set high by a low-to-high transition of clka when a port a read is selected and mba is high. mbf2 is set high when the device is reset. odd/ odd/even i odd parity is checked on each port when odd/ even is high, and even parity is checked when even parity select odd/ even is low. odd/ even also selects the type of parity generated for each port if parity generation is enabled for a read operation. pefa port a parity o when any byte applied to terminals a0-a35 fails parity, pefa is low. bytes are organized as a0-a8, error flag (port a) a9-a17, a18-a26, and a27-a35, with the most significant bit of each byte serving as the parity bit. the type of parity checked is determined by the state of the odd/ even input. the parity trees used to check the a0-a35 inputs are shared by the mail2 register to generate parity if parity generation is selected by pga. therefore, if a mail2 read with parity generation is setup by having w/ r a low, mba high, and pga high, the pefa flag is forced high regardless of the a0-a35 inputs. pefb port b parity o when any valid byte applied to terminals b0-b35 fails parity, pefb is low. bytes are organized as b0-b8, error flag (port b) b9-b17, b18-b26, b27-b35 with the most significant bit of each byte serving as the parity bit. a byte is vali d when it is used by the bus size selected for port b. the type of parity checked is determined by the state of the odd/ even input. the parity trees used to check the b0-b35 inputs are shared by the mail 1 register to generate parity if parity generation is selected by pgb. therefore, if a mail1 read with parity generation is setup by having w/ r b low, siz1 and siz0 high, and pgb high, the pefb flag is forced high regardless of the state of the b0- b35 inputs. pga port a parity i parity is generated for data reads from port a when pga is high. the type of parity generated is selected generation by the state of the odd/ even input. bytes are organized as a0-a8, a9-a17, a18-a26, and a27-a35. the generated parity bits are output in the most significant bit of each byte. pgb port b parity i parity is generated for data reads from port b when pgb is high. the type of parity generated is selected generation by the state of the odd/ even input. bytes are organized as b0-b8, b9-b17, b18-b26, and b27-b35. the generated parity bits are output in the most significant bit of each byte. rst reset i to reset the device, four low-to-high transitions of clka and four low-to-high transitions of clkb must occur while rst is low. this sets the afa , afb , mbf1 , and mbf2 flags high and the efa , efb , aea , aeb , ffa, and ffb flags low. the low-to-high transition of rst latches the status of the fs1 and fs0 inputs to select almost-full and almost-empty flag offsets. siz0, siz1 port b bus i a low-to-high transition of clkb latches the states of siz0, siz1, and be , and the following low-to-high size selects (port b) transition of clkb implements the latched states as a port b bus size. port b bus sizes can be long word, word or byte. a high on both siz0 and siz1 accesses the mailbox registers for a port b 36-bit write or read. sw0, sw1 port b byte i at the beginning of each long word transfer, one of four modes of byte-order swapping is selected by sw0 swap select (port b) and sw1. the four modes are no swap, byte swap, word swap, and byte-word swap. byte-order swapping is possible with any bus-size selection. w/ r a port a write/ i a high selects a write operation and a low selects a read operation on port a for a low-to-high read select transition of clka. the a0-a35 outputs are in the high-impedance state when w/ r a is high. w/ r b port b write/ i a high selects a write operation and a low selects a read operation on port b for a low-to-high read select transition of clkb. the b0-b35 outputs are in the high-impedance state when w/ r b is high.
6 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) symbol rating commercial unit v cc supply voltage range ?0.5 to +4.6 v v i (2) input voltage range ?0.5 to v cc +0.5 v v o (2) output voltage range ?0.5 to v cc +0.5 v i ik input clamp current, (v i < 0 or v i > v cc ) 20 ma i ok output clamp current, (v o < 0 or v o > v cc ) 50 ma i out continuous output current, (v o = 0 to v cc ) 50 ma i cc continuous current through v cc or gnd 500 ma t stg storage temperature range ?65 to 150 c notes: 1. stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress rat ings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to abso lute-maximum-rated conditions for extended periods may affect device reliability. 2. the input and output voltage ratings may be exceeded provided the input and output current ratings are observed. symbol parameter min. typ. max. unit v cc (1) supply voltage 3.0 3.3 3.6 v v ih high level input voltage 2 ? v cc +0.5 v v il low-level input voltage ? ? 0.8 v i oh high-level output current ?? ?4 ma i ol low-level output current ?? 8 ma t a operating free-air 0 ? 70 c temperature recommended operating conditions electrical characteristics over recommended operating free- air temperature range (unless otherwise noted) notes: 1. all typical values are at v cc = 3.3v, t a = 25 c. 2. for additional i cc information, see figure 1, typical characteristics: supply current (i cc ) vs. clock frequency (f s ) . IDT72V3614 commercial t clk = 12, 15, 20 ns symbol parameter test conditions min. typ. (1) max. unit v oh output logic "1" voltage v cc = 3.0v, i oh = ?4 ma 2.4 ? ? v v ol output logic "0" voltage v cc = 3.0v, i ol = 8 ma ? ? 0.5 v i li input leakage current (any input) v cc = 3.6v, v i = v cc or 0 ? ? 5 a i lo output leakage current v cc = 3.6v, v o = v cc or 0 ? ? 5 a i cc (2) standby current v cc = 3.6v, v i = v cc - 0.2v or 0 ? ? 500 a c in input capacitance v i = 0, f = 1 mhz ? 4 ? pf c out output capacitance v o = 0, f = 1 mhz ? 8 ? pf note: 1. for 12ns (83mhz operation), vcc=3.3v +/-0.15v, jedec jesd8-a compliant
7 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range determining active current consumption and power dissipation the i cc (f) current for the graph in figure 1 was taken while simultaneously reading and writing the fifo on the IDT72V3614 with clka and clkb set to f s . all data inputs and data outputs change state during each clock cycle to consume the highest supply current. data outputs wer e disconnected to normalize the graph to a zero-capacitance load. once the capacitive lead per data-output channel is known, the power dissipation can be c alculated with the equation below. calculating power dissipation with i cc(f ) taken from figure 1, the maximum power dissipation (p t ) of the IDT72V3614 can be calculated by: p t = v cc x i cc(f) + (c l x v oh 2 x f o ) n where: n = number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus-size) c l = output capacitance load f o = switching frequency of an output v oh = output high level voltage when no reads or writes are occurring on this device, the power dissipated by a single clock (clka or clkb) input running at fr equency f s is calculated by: p t =v cc x f s x 0.025 ma/mhz figure 1. typical characteristics: supply current (i cc ) vs. clock frequency (f s ) 010 20 30 40 50 60 70 0 25 50 75 100 125 150 v cc = 3.3v f s ? clock frequency ? mhz i cc(f) supply current ma f data = 1/2 f s t a = 25 c c l = 0 pf v cc = 3.0v 4663 drw 04 v cc = 3.6v 80 90 175
8 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range dc electrical characteristics over recommended ranges of supply voltage and operating free-air temperature IDT72V3614l12 IDT72V3614l15 IDT72V3614l20 symbol parameter min. max. min. max. min. max. unit f s clock frequency, clka or clkb ? 83 ? 66.7 ? 50 mhz t clk clock cycle time, clka or clkb 12 ? 15 ? 20 ? ns t clkh pulse duration, clka and clkb high 5 ? 6 ? 8 ? ns t clkl pulse duration, clka and clkb low 5 ? 6 ? 8 ? ns t ds setup time, a0-a35 before clka and b0-b35 before 4 ? 4 ? 5 ? ns clkb t ens setup time, csa , w/ r a, ena and mba before clka ; 3.5 ? 5 ? 5 ? ns csb ,w/ r b and enb before clkb t szs setup time, siz0, siz1,and be before clkb 3.5 ? 4 ? 5 ? ns t sws setup time, sw0 and sw1 before clkb 4?6? 7?ns t pgs setup time, odd/ even and pga before clka ;3?4?5?ns odd/ even and pgb before clkb (1) t rsts setup time, rst low before clka or clkb (2) 4?5? 6?ns t fss setup time, fs0 and fs1 before rst high 4 ? 5 ? 6 ? ns t dh hold time, a0-a35 after clka and b0-b35 after clkb 0.5 ? 1 ? 1 ? ns t enh hold time, csa , w/ r a, ena and mba after clka ; csb, 0.5 ? 1 ? 1 ? ns w/ r b, and enb after clkb t szh hold time, siz0, siz1, and be after clkb 1?1? 2?ns t swh hold time, sw0 and sw1 after clkb 1?1? 2?ns t pgh hold time, odd/ even and pga after clka ; odd/ even 0?0? 0?ns and pgb after clkb (1) t rsth hold time, rst low after clka or clkb (2) 4?5? 6?ns t fsh hold time, fs0 and fs1 after rst high 4 ? 4 ? 4 ? ns t skew1 (3) skew time, between clka and clkb for efa , efb , 5.5 ? 8 ? 8 ? ns ffa , and ffb t skew2 (3,4) skew time, between clka and clkb for aea , aeb ,14?14?16?ns afa , and afb notes: 1. only applies for a clock edge that does a fifo read. 2. requirement to count the clock edge as one of at least four needed to reset a fifo. 3. skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship b etween clka cycle and clkb cycle. 4. design simulated, not tested. commercial: vcc=3.3v 0.30v; for 12ns (83mhz) operation, vcc=3.3v 0.15v; t a = 0 c to +70 c; jedec jesd8-a compliant
9 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range switching characteristics over recommended ranges of supply voltage and operating free-air temperature, c l = 30 p f notes: 1. writing data to the mail1 register when the b0-b35 outputs are active and siz1, siz0 are high. 2. writing data to the mail2 register when the a0-a35 outputs are active and mba is high. 3. only applies when a new port b bus size is implemented by the rising clkb edge. 4. only applies when reading data from a mail register. IDT72V3614l12 IDT72V3614l15 IDT72V3614l20 symbol parameter min. max. min. max. min. max. unit t a access time, clka to a0-a35 and clkb to b0-b35 1 8 2 10 2 12 ns t wff propagation delay time, clka to ffa and clkb to ffb 18210212ns t ref propagation delay time, clka to efa and and clkb 18210212ns to efb t pae propagation delay time, clka to aea and clkb to aeb 18210212ns t paf propagation delay time, clka to afa and clkb to afb 18210212ns t pmf propagation delay time, clka to mbf1 low or mbf2 1819112ns high and clkb to mbf2 low or mbf1 high t pmr propagation delay time, clka to b0-b35 (1) 28210212ns and clkb to a0-a35 (2) t ppe (3) propagation delay time, clkb to pefb 28210212ns t mdv propagation delay time, mba to a0-a35 valid and siz1, 1 8 1 10 1 11. 5 ns siz0 to b0-b35 valid t pdpe propagation delay time, a0-a35 valid to pefa valid; 2 8 2 10 2 11 ns b0-b35 valid to pefb valid t pope propagation delay time, odd/ even to pefa and pefb 28210212ns t popb (4) propagation delay time, odd/ even to parity bits (a8, a17, 2 8 2 10 2 12 ns a26, a35) and (b8, b17, b26, b35) t pepe propagation delay time, csa , ena,w/ r a, mba, or pga to 1 8 1 10 1 12 ns pefa ; csb , enb, w/ r b, siz1, siz0, or pgb to pefb t pepb (4) propagation delay time, csa , ena, w/ r a, mba, or pga to 2 8 2 10 2 12 ns parity bits (a8, a17, a26, a35); csb, enb, w/ r b,siz1, siz0, or pgb to parity bits (b8, b17, b26, b35) t rsf propagation delay time, rst to ( mbf1 , mbf2 ) high 1 10 1 15 1 20 ns t en enable time, csa and w/ r a low to a0-a35 active and csb 26210212ns low and w /rb high to b0-b35 active t dis disable time, csa or w/ r a high to a0-a35 at high- 1 6 1 8 1 9 ns impedance and csb high or w /rb low to b0-b35 at high-impedance commercial: vcc=3.3v 0.30v; for 12ns (83mhz) operation, vcc=3.3v 0.15v; t a = 0 c to +70 c; jedec jesd8-a compliant
10 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range output register. when the empty flag is low, the fifo is empty and attempted fifo reads are ignored. when reading fifo1 with a byte or word size on port b, efb is set low when the fourth byte or second word of the last long word is read. the read pointer of a fifo is incremented each time a new word is clocked to the output register. the state machine that controls an empty flag monitors a write-pointer and read-pointer comparator that indicates when the fifo memory status is empty, empty+1, or empty+2. a word written to a fifo can be read to the fifo output register in a minimum of three cycles of the empty flag synchronizing clock. therefore, an empty flag is low if a word in memory is the next data to be sent to the fifo output register and two cycles of the port clock that reads data from the fifo have not elapsed since the time the word was written. the empty flag of the fifo is set high by the second low-to- high transition of the synchronizing clock, and the new data word can be read to the fifo output register in the following cycle. a low-to-high transition on an empty flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time t skew1 or greater after the write. otherwise, the subsequent clock cycle can be the first synchronization cycle (see figure 14 and 15). full flag ( ffa , ffb ) the full flag of a fifo is synchronized to the port clock that writes data to its array. when the full flag is high, a memory location is free in the fifo to receive new data. no memory locations are free when the full flag is low and attempted writes to the fifo are ignored. each time a word is written to a fifo, the write pointer is incremented. the state machine that controls a full flag monitors a write-pointer and read-pointer comparator that indicates when the fifo memory status is full, full-1, or full-2. from the time a word is read from a fifo, the previous memory location is ready to be written in a minimum of three cycles of the full flag synchronizing clock. therefore, a full flag is low if less than two cycles of the full flag synchronizing clock have elapsed since the next memory write location has been read. the second low-to-high transition on the full flag synchronization clock after the read sets the full flag high and the data can be written in the following clock cycle. a low-to-high transition on a full flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t skew1 or greater after the read. otherwise, the subsequent clock cycle can be the first synchronization cycle (see figure 16 and 17). almost-empty flags ( aea , aeb ) the almost-empty flag of a fifo is synchronized to the port clock that reads data from its array. the state machine that controls an almost-empty flag monitors a write-pointer and a read-pointer comparator that indicates when the fifo memory status is almost-empty, almost-empty+1, or almost-empty+2. the almost-empty state is defined by the value of the almost-full and almost-empty offset register (x). this register is loaded with one of four preset values during a device reset (see reset section). an almost-empty flag is low when the fifo contains x or less long words in memory and is high when the fifo contains (x+1) or more long words. two low-to-high transitions of the almost-empty flag synchronizing clock are required after a fifo write for the almost-empty flag to reflect the new level of fill. therefore, the almost-empty flag of a fifo containing (x+1) or more long words remains low if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (x+1) level. an almost-empty flag is set high by the second low-to-high transition of the synchronizing clock after the fifo write that fills memory to the (x+1) level. a low-to-high transition of an almost-empty flag synchronizing clock begins the first synchronization signal descriptions reset the IDT72V3614 is reset by taking the reset ( rst ) input low for at least four port a clock (clka) and four port b clock (clkb) low-to-high transitions. the reset input can switch asynchronously to the clocks. a device reset initializes the internal read and write pointers of each fifo and forces the full flags ( ffa , ffb ) low, the empty flags ( efa , efb ) low, the almost-empty flags ( aea , aeb ) low and the almost-full flags ( afa , afb ) high. a reset also forces the mailbox flags ( mbf1 , mbf2 ) high. after a reset, ffa is set high after two low-to-high transitions of clka and ffb is set high after two low-to-high transitions of clkb. the device must be reset after power up before data is written to its memory. a low-to-high transition on the rst input loads the almost-full and almost-empty offset register (x) with the values selected by the flag select (fs0, fs1) inputs. the values that can be loaded into the registers are shown in table 1. for the relevant reset and preset value loading timing diagram, see figure 5. fifo write/read operation the state of port a data a0-a35 outputs is controlled by the port a chip select ( csa ) and the port a write/read select (w/ r a). the a0-a35 outputs are in the high-impedance state when either csa or w/ r a is high. the a0-a35 outputs are active when both csa and w/ r a are low. data is loaded into fifo1 from the a0-a35 inputs on a low-to-high transition of clka when csa is low, w/ r a is high, ena is high, mba is low, and ffa is high. data is read from fifo2 to the a0-a35 outputs by a low-to-high transition of clka when csa is low, w/ r a is low, ena is high, mba is low, and efa is high (see table 2). port a read and write timing diagrams can be found in figure 6 and 15. the port b control signals are identical to those of port a. the state of the port b data (b0-b35) outputs is controlled by the port b chip select ( csb ) and the port b write/read select (w/ r b). the b0-b35 outputs are in the high- impedance state when either csb or w/ r b is high. the b0-b35 outputs are active when both csb and w/ r b are low. data is loaded into fifo2 from the b0-b35 inputs on a low-to-high transition of clkb when csb is low, w/ r b is high, enb is high, efb is high, and either siz0 or siz1 is low. data is read from fifo1 to the b0-b35 outputs by a low-to-high transition of clkb when csb is low, w/ r b is low, enb is high, efb is high, and either siz0 or siz1 is low (see table 3). port b read and write timing diagrams together with bus-matching, byte-swapping and endian select can be found in figures 7 to 12. the setup and hold time constraints to the port clocks for the port chip selects ( csa , csb ) and write/read selects (w/ r a, w/ r b) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. if a port enable is low during a clock cycle, the port chip select and write/read select can change states during the setup and hold time window of the cycle. synchronized fifo flags each fifo is synchronized to its port clock through two flip-flop stages. this is done to improve flag reliability by reducing the probability of metastable events on the output when clka and clkb operate asynchronously to one another. efa , aea , ffa , and afa are synchronized to clka. efb , aeb , ffb , and afb are synchronized to clkb. tables 4 and 5 show the relationship of each port flag to fifo1 and fifo2. empty flags ( efa , efb ) the empty flag of a fifo is synchronized to the port clock that reads data from its array. when the empty flag is high, new data can be read to the fifo
11 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range csb w/ r b enb siz1, siz0 clkb data b (b0-b35) i/o port functions h x x x x input none l h l x x input none l h h one, both low input fifo2 write l h h both high input mail2 write l l l one, both low x output none l l h one, both low output fifo1 read l l l both high x output none l l h both high output mail1 read (set mbf1 high) table 3 C port-b enable function table csa w/ r a ena mba clka data a (a0-a35) i/o port functions h x x x x input none l h l x x input none lh h l input fifo1 write lh h h input mail1 write l l l l x output none ll h l output fifo2 read l l l h x output none ll h h output mail2 read (set mbf2 high) table 2 C port-a enable function table almost-full and fs1 fs0 rst almost-empty flag offset register (x) hh 16 hl 12 lh 8 ll 4 table 1 C flag programming synchronized synchronized number of 36-bit to clkb to clka words in the fifo1 (1) efb aeb afa ffa 0llhh 1 to x h l h h (x+1) to [64-(x+1)] h h h h (64-x) to 63 h h l h 64 h h l l table 4 C fifo1 flag operation synchronized synchronized number of 36-bit to clka to clkb words in the fifo2 (1) efa aea afb ffb 0llhh 1 to x h l h h (x+1) to [64-(x+1)] h h h h (64-x) to 63 h h l h 64 h h l l table 5 C fifo2 flag operation note: 1. x is the value in the almost-empty flag and almost-full flag offset register.
12 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range the levels applied to the port b bus size select (siz0, siz1) inputs and the big-endian select ( be ) input are stored on each clkb low-to-high transition. the stored port b bus size selection is implemented by the next rising edge on clkb according to figure 2. only 36-bit long-word data is written to or read from the two fifo memories on the IDT72V3614. bus-matching operations are done after data is read from the fifo1 ram and before data is written to the fifo2 ram. port b bus sizing does not apply to mail register operations. bus-matching fifo1 reads data is read from the fifo1 ram in 36-bit long word increments. if a long word bus size is implemented, the entire long word immediately shifts to the fifo1 output register. if byte or word size is implemented on port b, only the first one or two bytes appear on the selected portion of the fifo1 output register, with the rest of the long word stored in auxiliary registers. in this case, subsequent fifo1 reads with the same bus-size implementation output the rest of the long word to the fifo1 output register in the order shown by figure 2. each fifo1 read with a new bus-size implementation automatically unloads data from the fifo1 ram to its output register and auxiliary registers. therefore, implementing a new port b bus size and performing a fifo1 read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread long word data. when reading data from fifo1 in byte or word format, the unused b0-b35 outputs are indeterminate. bus-matching fifo2 writes data is written to the fifo2 ram in 36-bit long word increments. fifo2 writes, with a long-word bus size, immediately store each long word in fifo2 ram. data written to fifo2 with a byte or word bus size stores the initial bytes or words in auxiliary registers. the clkb rising edge that writes the fourth byte or the second word of long word to fifo2 also stores the entire long word in fifo2 ram. the bytes are arranged in the manner shown in figure 2. each fifo2 write with a new bus-size implementation resets the state machine that controls the data flow from the auxiliary registers to the fifo2 ram. therefore, implementing a new bus size and performing a fifo2 write before bytes or words stored in the auxiliary registers have been loaded to fifo2 ram results in a loss of data. when writing data to fifo2 in byte or word format, the unused b0-b35 inputs are don't care (1) inputs. port-b mail register access in addition to selecting port-b bus sizes for fifo reads and writes, the port b bus size select (siz0, siz1) inputs also access the mail registers. when both siz0 and siz1 are high, the mail1 register is accessed for a port b long word read and the mail2 register is accessed for a port b long word write. the mail register is accessed immediately and any bus-sizing operation that may be underway is unaffected by the mail register access. after the mail register access is complete, the previous fifo access can resume in the next clkb cycle. the logic diagram in figure 3 shows the previous bus-size selection is preserved when the mail registers are accessed from port b. a port b bus size is implemented on each rising clkb edge according to the states of siz0_q, siz1_q, and be _q. byte swapping the byte-order arrangement of data read from fifo1 or data written to fifo2 can be changed synchronous to the rising edge of clkb. byte-order swapping is not available for mail register data. four modes of byte-order swapping (including no swap) can be done with any data port size selection. cycle if it occurs at time t skew2 or greater after the write that fills the fifo to (x+1) long words. otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see figure 18 and 19). almost full flags ( afa , afb ) the almost-full flag of a fifo is synchronized to the port clock that writes data to its array. the state machine that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the fifo memory status is almost full, almost full-1, or almost full-2. the almost-full state is defined by the value of the almost-full and almost-empty offset register (x). this register is loaded with one of four preset values during a device reset (see reset section). an almost-full flag is low when the fifo contains (64-x) or more long words in memory and is high when the fifo contains [64-(x+1)] or less long words. two low-to-high transitions of the almost-full flag synchronizing clock are required after a fifo read for the almost-full flag to reflect the new level of fill. therefore, the almost-full flag of a fifo containing [64-(x+1)] or less words remains low if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of long words in memory to [64-(x+1)]. an almost-full flag is set high by the second low-to-high transition of the synchronizing clock after the fifo read that reduces the number of long words in memory to [64-(x+1)]. a low-to-high transition of an almost-full flag synchronizing clock begins the first synchronization cycle if it occurs at time t skew2 or greater after the read that reduces the number of long words in memory to [64-(x+1)]. otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see figure 20 and 21). mailbox registers each fifo has a 36-bit bypass register to pass command and control information between port a and port b without putting it in queue. the mailbox select (mba, siz0, siz1) inputs choose between a mail register and a fifo for a port data transfer operation. a low-to-high transition on clka writes a0-a35 data to the mail1 register when a port a write is selected by csa , w/ r a, and ena with mba high. a low-to-high transition on clkb writes b0- b35 data to the mail2 register when a port b write is selected by csb , w/ r b, and enb with both siz1 and siz0 high. writing data to a mail register sets the corresponding flag ( mbf1 or mbf2 ) low. attempted writes to a mail register are ignored while the mail flag is low. when the port a data outputs (a0-a35) are active, the data on the bus comes from the fifo2 output register when mba is low and from the mail2 register when mba is high. when the port b data outputs (b0-b35) are active, the data on the bus comes from the fifo1 output register when either one or both siz1 and siz0 are low and from the mail2 register when both siz1 and siz0 are high. the mail1 register flag ( mbf1 ) is set high by a rising clkb edge when a port b read is selected by csb , w/ r b, and enb with both siz1 and siz0 high. the mail2 register flag ( mbf2 ) is set high by a low-to-high transition on clka when port a read is selected by csa , w/ r a, and ena and mba is high. the data in the mail register remains intact after it is read and changes only when new data is written to the register. relevant mail register and mail register flag timing diagrams can be found in figure 22 and figure 23. dynamic bus sizing the port b bus can be configured in a 36-bit long word, 18-bit word, or 9- bit byte format for data read from fifo1 or written to fifo2. word- and byte- size bus selections can utilize the most significant bytes of the bus (big-endian) or least significant bytes of the bus (little-endian). port b bus size can be changed dynamically and synchronous to clkb to communicate with peripherals of various bus widths.
13 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range the order of the bytes are rearranged within the long word, but the bit order within the bytes remains constant. byte arrangement is chosen by the port b swap select (sw0, sw1) inputs on a clkb rising edge that reads a new long word from fifo1 or writes a new long word to fifo2. the byte order chosen on the first byte or first word of a new long word read from fifo1 or written to fifo2 is maintained until the entire long word is transferred, regardless of the sw0 and sw1 states during subsequent writes or reads. figure 4 is an example of the byte-order swapping available for long words. performing a byte swap and bus size simultaneously for a fifo1 read first rearranges the bytes as shown in figure 4, then outputs the bytes as shown in figure 2. simultaneous bus-sizing and byte-swapping operations for fifo2 writes, first loads the data according to figure 2, then swaps the bytes as shown in figure 4 when the long word is loaded to fifo2 ram. parity checking the port a inputs (a0-a35) and port b inputs (b0-b35) each have four parity trees to check the parity of incoming (or outgoing) data. a parity failure on one or more bytes of the port a data bus is reported by a low level on the port parity error flag ( pefa ). a parity failure on one or more bytes of the port b data input that are valid for the bus-size implementation is reported by a low level on the port b parity error flag ( pefb ). odd or even parity checking can be selected, and the parity error flags can be ignored if this feature is not desired. parity status is checked on each input bus according to the level of the odd/ even parity (odd/ even ) select input. a parity error on one or more valid bytes of a port is reported by a low level on the corresponding port parity error flag ( pefa , pefb ) output. port a bytes are arranged as a0-a8, a9-a17, a18-a26, and a27-a35. port b bytes are arranged as b0-b8, b9-b17, b18-b26, and b27-b35, and its valid bytes are those used in a port b bus-size implementation. when odd/even parity is selected, a port parity error flag ( pefa , pefb ) is low if any byte on the port has an odd/even number of low levels applied to the bits. the four parity trees used to check the a0-a35 inputs are shared by the mail2 register when parity generation is selected for port a reads (pga = high). when a port a read from the mail2 register with parity generation is selected with csa low, ena high, w/ r a low, mba high, and pga high, the port a parity error flag ( pefa ) is held high regardless of the levels applied to the a0-a35 inputs. likewise, the parity trees used to check the b0-b35 inputs are shared by the mail1 register when parity generation is selected for port b reads (pgb = high). when a port b read from the mail1 register with parity generation is selected with csb low, enb high, w/ r b low, both siz0 and siz1 high, and pgb high, the port b parity error flag ( pefb ) is held high regardless of the levels applied to the b0-b35 inputs (see figure 24 and 25). parity generation a high level on the port a parity generate select (pga) or port b parity generate select (pgb) enables the IDT72V3614 to generate parity bits for port reads from a fifo or mailbox register. port a bytes are arranged as a0-a8, a9-a17, a18-26, and a27-a35, with the most significant bit of each byte used as the parity bit. port b bytes are arranged as b0-b8, b9-b17, b18-b26, and b27-b35, with the most significant bit of each byte used as the parity bit. a write to a fifo or mail register stores the levels applied to all nine inputs of a byte regardless of the state of the parity generate select (pga, pgb) inputs. when data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the odd/ even select. the generated parity bits are substituted for the levels originally written to the most significant bits of each byte as the word is read to the data outputs. parity bits for fifo data are generated after the data is read from sram and before the data is written to the output register. therefore, the port a parity generate select (pga) and odd/even parity select (odd/ even ) have setup and hold time constraints to the port a clock (clka) and the port b parity generate select (pgb) and odd/ even have setup and hold-time constraints to the port b clock (clkb). these timing constraints only apply for a rising clock edge used to read a new long word to the fifo output register. the circuit used to generate parity for the mail1 data is shared by the port b bus (b0-b35) to check parity and the circuit used to generate parity for the mail2 data is shared by the port a bus (a0-a35) to check parity. the shared parity trees of a port are used to generate parity bits for the data in a mail register when the port chip select ( csa , csb ) is low, enable (ena, enb) is high, write/read select (w/ r a, w/ r b) input is low, the mail register is selected (mba is high for port a; both siz0 and siz1 are high for port b), and port parity generate select (pga, pgb) is high. generating parity for mail register data does not change the contents of the register (see figure 26 and 27).
14 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range figure 2. dynamic bus sizing a35 ? a27 a26 ? a18 a1 ? a9 a8 ? a0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 a a b b c c (a) long word size (b) word size ? big-endian (c) word size ? little-endian (d) byte size ? big-endian write to fifo1/ read from fifo2 read from fifo1/ write to fifo2 1st: read from fifo1/ write to fifo2 2nd: read from fifo1/ write to fifo2 1st: read from fifo1/ write to fifo2 2nd: read from fifo1/ write to fifo2 1st: read from fifo1/ write to fifo2 2nd: read from fifo1/ write to fifo2 3rd: read from fifo1/ write to fifo2 4th: read from fifo1/ write to fifo2 b e siz1 siz0 b e siz1 siz0 b e siz1 siz0 b e siz1 siz0 l l h h l h l h l x l l byte order on port a: 4663 drw fig 01 d d ab c d c d ab a b c d byte order on port b: b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0
15 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range figure 2. dynamic bus sizing (continued ) (1) either a high or low can be applied to a "don't care" input with no change to the logical operation of the fifo. neverthele ss, inputs that are temporarily "don't care" (along with unused inputs) must not be left open, rather they must be either high or low. figure 3. logic diagrams for siz0, siz1, and be register d c (d) byte size ? little-endian 1st: read from fifo1/ write to fifo2 2nd: read from fifo1/ write to fifo2 a b 3rd: read from fifo1/ write to fifo2 4th: read from fifo1/ write to fifo2 b e siz1 siz0 h h l 4663 drw fi g 01a b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 mux g1 1 1 d q siz0 q siz1 q be q siz0 siz1 be clkb 4663 drw fig 02
16 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range figure 4. byte swapping (long word size example) a a a d a c a b b b c b d b a b c c c b c a c d d d d a d b d c (a) no swap (b) byte swap (c) word swap (d) byte-word swap l l sw1 sw0 sw1 sw0 sw1 sw0 sw1 sw0 l l l h h l h h 4663 drw fi g 03 a35 ? a27 a26 ? a18 a17 ? a9 a8 ? a0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 a35 ? a27 a26 ? a18 a17 ? a9 a8 ? a0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 a35 ? a27 a26 ? a18 a17 ? a9 a8 ? a0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0 a35 ? a27 a26 ? a18 a17 ? a9 a8 ? a0 b35 ? b27 b26 ? b18 b17 ? b9 b8 ? b0
17 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range figure 5. device reset and loading the x register with the value of eight clka rst ffa ffb efb aea clkb efa fs1,fs0 4663 drw 05 t rsts t rsth t fsh t fss t wff t wff t wff 0,1 t ref t ref afa mbf1 , mbf2 t wff t rsf t pae aeb afb t paf t pae t paf
18 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range note: 1. siz0 = high and siz1 = high writes data to the mail2 register swap mode data written to fifo2 data read from fifo2 sw1 sw0 b35-27 b26-18 b17-b9 b8-b0 a35-27 a26-a18 a17-a9 a8-a0 llab cdabcd lhdc baabcd hlcd ababcd hhba dcabcd data swap table for long-word writes to fifo2 figure 7. port-b long-word write cycle timing for fifo2 figure 6. port-a write cycle timing for fifo1 clkb enb sw1, sw0 ffb w/ r b b0-b35 be pefb odd/ even high 4663 drw 07 t ens t ens t ens t enh csb siz1, siz0 valid valid t pdpe not (1,1) (1) (0,0) t dh t ds t szh t szs t szs t szh t ens t enh t ppe (0,0) t sws t swh 4663 drw 06 clka ffa ena a0 - a35 mba csa w/ r a t clkh t clkl t clk t ens t ens t ens t ens t ds t enh t enh t enh t enh t dh w1 (1) w2 (1) t ens t enh t enh t ens no operation odd/ even pefa valid valid t pdpe t pdpe high note: 1. written to fifo1.
19 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range notes: 1. siz0 = high and siz1 = high writes data to the mail2 register. 2. pefb indicates parity error for the following bytes: b35-b27 and b26-b18 for big-endian bus, and b17-b9 and b-8-b0 for little-endia n bus. figure 8. port-b word write cycle timing for fifo2 data written to fifo2 swap write data read from fifo2 mode no. big-endian little-endian sw1 sw0 b35-27 b26-18 b17-b9 b8-b0 a35-27 a26-a18 a17-a9 a8-a0 ll1 ab c d a bcd 2cda b lh1 dc b a a bcd 2bad c hl1 cd a b a bcd 2abc d hh1 ba d c a bcd 2dcb a data swap table for word writes to fifo2 clkb sw1, sw0 enb ffb w/ r b be high 4663 drw 08 pefb odd/ even big- endian b18-b35 little- endian b0-b17 siz1, siz0 csb (0, 1) not (1,1) (1) t enh t enh t ens t ens t enh t ens t ens t swh t szh t szh t szh t szs t szs t szs t szs t ds t ds valid valid t pdpe t ppe t dh t dh t szh t sws (0, 1)
20 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range notes: 1. siz0 = high and siz1 = high writes data to the mail2 register. 2. pefb indicates parity error for the following bytes: b35?b27 for big-endian bus and b8?b0 for little-endian bus. data written to fifo2 swap write data read from fifo2 mode no. big-endian little-endian sw1 sw0 b35-b27 b8-80 a35-a27 a26-a18 a17-a9 a8-a0 1a d ll 2 b ca b cd 3c b 4d a 1d a lh 2 c ba b cd 3b c 4a d 1c b hl 2 d aa b cd 3a d 4b c 1b c hh 2 a da b cd 3d a 4c b data swap table for byte writes to fifo2 figure 9. port-b byte write cycle timing for fifo2 ffb csb w/ r b siz1, siz0 clkb 4663 drw 09 high sw1, sw0 be odd/ even b0- b8 (1,0) (1,0) not (1,1) (1) t ens t enh t sws t szh t szh t szs enb little- endian valid valid valid valid big- endian b27- b35 pefb t ppe t pdpe t pdpe t pdpe t ds t ds t dh t dh t ens t ens t szh t szs t szs t szs t szh t enh t enh t ens t enh (1,0) (1,0)
21 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range notes: 1. siz0 = high and siz1 = high selects the mail1 register for output on b0-b35. 2. data read from fifo1. data written to fifo1 swap mode data read from fifo1 a35-a27 a26-a18 a17-a9 a8-a0 sw1 sw0 b35-b27 b26-b18 b17-b9 b8-b0 abcd lla bcd abcd lhd cba abcd hlc dab abcd hhb adc data swap table for fifo long-word reads from fifo1 figure 10. port-b long-word read cycle timing for fifo1 clkb enb sw1, sw0 efb w/ r b pgb, be odd/ even high 4663 drw 10 csb siz1, siz0 not (1,1) (1) t pgh t pgs t szh t szs t szs t szh t enh (0,0) t sws b0-b35 not (1,1) (1) previous data w1 (2) w2 (2) t dis t a t a t en t ens t enh t swh t ens no operation (0,0)
22 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range notes: 1. siz0 = high and siz1 = high selects the mail1 register for output on b0-b35. 2. unused word b0-b17 or b18-b35 are indeterminate. data read from fifo1 data written to fifo1 swap mode read no. big-endian little-endian a35-a27 a26-a18 a17-a9 a8-a0 sw1 sw0 b35-b27 b26-b18 b17-b9 b8-b0 1a b cd ab c d l l 2 c d a b 1d c ba ab c d l h 2 b a d c 1c d ab ab c d h l 2 a b c d 1b a dc ab c d h h 2 d c b a data swap table for word reads from fifo1 figure 11. port-b word read cycle timing for fifo1 t dis clkb enb sw1, sw0 efb w/ r b pgb, be odd/ even high 4663 drw 11 csb siz1, siz0 not (1,1) (1) t pgh t pgs t szh t szs t szs t szh (0,1) t sws b0-b17 not (1,1) (1) previous data t dis t a t a t en t ens t enh t swh no operation previous data b18-b35 little- endian big- endian t a t a read 1 read 1 read 2 read 2 (0,1) (2) (2)
23 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range notes: 1. siz0 = high and siz1 = high selects the mail1 register for output on b0-b35. 2. unused bytes b9-b35 or b0-b26 are indeterminate. figure 12. port-b byte read cycle timing for fifo1 data written to fifo 1 swap mode read big- little- no. endian endian a35-a27 a26-a18 a17-a9 a8-a0 sw1 sw0 b35-b27 b8-b0 1ad 2bc abcdll3 cb 4da 1da 2cb ab c d l h 3 b c 4ad 1cb 2da abcdhl 3 ad 4bc 1bc 2ad abcdhh3 da 4cb data read from fifo 1 data swap table for byte reads from fifo1 efb csb w/ r b siz1, siz0 enb clkb 4663 drw 12 high sw1, sw0 be pgb, odd/ even b0-b8 b27-b35 read 4 read 1 read 2 read 4 read 1 read 3 read 3 previous data previous data read 2 (1,0) (1,0) (1,0) not (1,1) (1) no operation t dis t dis t a t a t a t a t a t a t en t pgh t pgs not (1,1) (1) not (1,1) (1) not (1,1) (1) (1,0) t ens t enh t sws t swh t szh t szh t szs t szs t a t a little- endian big- endian (2) (2)
24 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range note: 1. read from fifo2. figure 13. port-a read cycle timing for fifo2 notes: 1. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for efb to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew1 , then the transition of efb high may occur one clkb cycle later than shown. 2. port-b size of long word is selected for fifo1 read by siz1 = low, siz0 = low. if port-b size is word or byte, efb is set low by the last word or byte read from fifo1, respec- tively. figure14. efb flag timing and first data read when fifo1 is empty 4663 drw 13 clka efa ena a0 - a35 mba csa w/ r a t clk t clkh t clkl t ens t a t mdv t en t a t ens t enh t ens t enh previous data word 1 word 2 (1) (1) t enh t dis no operation pga, odd/ even high t pgh t pgs t pgh t pgs csa w r a mba ffa a0 - a35 clkb efb csb w/ r b siz1, siz0 ena enb b0 -b35 clka 12 4663 drw 14 t clkh t clkl t clk t ens t ens t enh t enh t ds t dh t skew1 t clk t clkl t ens t enh t a w1 fifo1 empty low high low low low t clkh w1 high (1) t ref t ref
25 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range notes: 1. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for efa to transition high in the next clka cycle. if the time between the rising clkb edge and rising clka edge is less than t skew1 , then the transition of efa high may occur one clka cycle later than shown. 2. port b size of long word is selected for fifo2 write by siz1 = low, siz0 = low. if port b size is word or byte t skew1 is referenced to the rising clkb edge that writes the last word or byte of the long word, respectively. figure 15. efa flag timing and first data read when fifo2 is empty csb w r b siz1, siz0 ffb b0 - b35 clka efa csa w/ r a mba enb ena a0 - a35 clkb 12 4663 drw 15 t clkh t clkl t clk t ens t ens t enh t enh t ds t dh t skew1 t clk t clkl t ens t enh t a w1 fifo2 empty low high low low low t clkh w1 high (1) t ref t ref
26 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range notes: 1. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for ffa to transition high in the next clka cycle. if the time between the rising clkb edge and rising clka edge is less than t skew1 , then ffa may transition high one clka cycle later than shown. 2. port b size of long word is selected for fifo1 read by siz1 = low, siz0 = low. if port b size is word or byte, t skew1 is referenced from the rising clkb edge that reads the last word or byte of the long word, respectively. figure 16. ffa flag timing and first available write when fifo1 is full. csb efb siz1, siz0 enb b0 - b35 clkb ffa clka csa 4663 drw 16 w r a 12 a0 - a35 mba ena t clk t clkh t clkl t ens t enh t a t skew1 t clk t clkh t clkl t ens t ens t ds t enh t enh t dh to fifo1 previous word in fifo1 output register next word from fifo1 low w/ r b low low high low high (1) fifo1 full t wff t wff
27 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range figure 17. ffb flag timing and first available write when fifo2 is full notes: 1. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for aeb to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew2 , then aeb may transition high one clkb cycle later than shown. 2. fifo1 write ( csa = low, w/ r a = high, mba = low), fifo1 read ( csb = low, w/ r b = low, either siz1 = low or siz0 = low). 3. port b size of long word is selected for fifo1 read by siz1 = low, siz0 = low. if port b size is word or byte, aeb is set low by the last word or byte read of the long word, respectively. figure 18. timing for aeb when fifo1 is almost-empty csa efa mba ena a0 - a35 clka ffb clkb csb 4663 drw 17 w r b 12 b0 - b35 siz1, siz0 enb t clk t clkh t clkl t ens t enh t a t skew1 t clk t clkh t clkl t ens t ens t ds t enh t enh t dh to fifo2 previous word in fifo2 output register next word from fifo2 low w/ r a low low high low high (1) fifo2 full t wff t wff aeb clka enb 4663 drw 18 ena clkb 2 1 t ens t enh t skew2 t pae t pae t ens t enh x long word in fifo1 (x+1) long words in fifo1 (1) notes: 1. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for ffb to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew1 , then ffb may transition high one clkb cycle later than shown. 2. port b size of long word is selected for fifo2 write by siz1 = low, siz0 = low. if port b size is word or byte, ffb is set low by the last word or byte write of the long word, respectively.
28 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range notes: 1. t skew2 is the minimum time between a rising clkb edge and a rising clka edge for aea to transition high in the next clka cycle. if the time between the rising clkb edge and rising clka edge is less than t skew2, then aea may transition high one clka cycle later than shown. 2. fifo2 write ( csb = low, w/ r b = high, either siz0 = low or siz1 = low), fifo2 read ( csa = low, w/ r a = low, mba = low). 3. port b size of long word is selected for fifo2 write by siz1 = low, siz0 = low. if port b size is word or byte, t skew2 is referenced from the rising clkb edge that writes the last word or byte of the long word, respectively. figure 19. timing for aea when fifo2 is almost-empty notes: 1. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for afa to transition high in the next clka cycle. if the time between the rising clka edge and rising clkb edge is less than t skew2 , then afa may transition high one clka cycle later than shown. 2. fifo1 write ( csa = low, w/ r a = high, mba = low), fifo1 read ( csb = low, w/ r b = low, either siz0 = low or siz1 = low). 3. port b size of long word is selected for fifo1 read by siz1 = low, siz0 = low. if port b size is word or byte, t skew2 is referenced from the last word or byte read of the long word, respectively. figure 20. timing for afa when fifo1 is almost-full notes: 1. t skew2 is the minimum time between a rising clkb edge and a rising clka edge for afb to transition high in the next clkb cycle. if the time between the rising clkb edge and rising clka edge is less than t skew2 , then afb may transition high one clkb cycle later than shown. 2. fifo2 write ( csb = low, w/ r b = high, either siz0 = low or siz1 = low), fifo2 read ( csa = low, w/ r a = low, mba = low). 3. port b size of long word is selected for fifo2 write by siz1 = low, siz0 = low. if port b size is word or byte, afb is set low by the last word or byte read of the long word, respectively. figure 21. timing for afb when fifo2 is almost-full aea clkb ena 4663 drw 19 enb clka 2 1 t ens t enh t skew2 t pae t pae t ens t enh (x+1) long words in fifo2 x long words in fifo2 (1) afa clka enb 4663 drw 20 ena clkb 12 t skew2 t ens t enh t paf t ens t enh t paf [64-(x+1)] long words in fifo1 (64-x) long words in fifo1 (1) afb clkb ena 4663 drw 21 enb clka 12 t skew2 t ens t enh t ens t enh t paf [64-(x+1)] long words in fifo2 (64-x) long words in fifo2 (1) t paf
29 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range note: 1. port b parity generation off (pgb = low). figure 22. timing for mail1 register and mbf1 flag 4663 drw 22 clka ena a0 - a35 mba csa w/ r a clkb mbf1 csb siz1, siz0 enb b0 - b35 w/ r b w1 t ens t enh t ds t dh t pmf t pmf t en t mdv t pmr t ens t enh t dis w1 (remains valid in mail1 register after read) fifo1 output register
30 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range note: 1. port-a parity generation off (pga = low). figure 24. odd/ even . w/ r a, mba, and pga to pefa timing figure 23. timing for mail2 register and mbf2 flag 4663 drw 23 clkb enb b0 - b35 siz1, siz0 csb w/ r b clka mbf2 csa mba ena a0 - a35 w/ r a w1 t ens t enh t ds t dh t pmf t pmf t ens t enh t dis t en t mdv t pmr fifo2 output register w1 (remains valid in mail2 register after read) t szs t szh 4663 drw 24 odd/ even pefa pga mba w/ r a valid valid valid valid t pope t pepe t pope t pepe
31 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range figure 25. odd/ even . w/ r b, siz1, siz0, and pgb to pefb timing figure 27. parity generation timing when reading from the mail1 register figure 26. parity generation timing when reading from the mail2 register note: 1. ena is high. note: 1. enb is high. 4663 drw 25 odd/ even pefb pgb siz1, siz0 w/ r b valid valid valid valid t pope t pepe t pope t pepe 4663 drw 26 odd/ even a8, a17, a26, a35 pga mba w/ r a mail2 data generated parity generated parity mail2 data csa low t en t pepb t popb t pepb t mdv 4663 drw 27 odd/ even b8, b17, b26, b35 pgb siz1, siz0 w/ r b mail1 data generated parity generated parity mail1 data csb low t en t pepb t popb t pepb t mdv
32 IDT72V3614 3.3v, cmos syncbififo tm with bus-matching and byte swapping 64 x 36 x 2 commercial temperature range note: 1. includes probe and jig capacitance. figure 28. load circuit and voltage waveforms 4663 drw 28 parameter measurement information from output under test 30 pf 330 ? 3.3v 510 ? load circuit 3 v gnd timing input data, enable input gnd 3 v 1.5 v 1.5 v voltage waveforms setup and hold times voltage waveforms pulse durations voltage waveforms enable and disable times voltage waveforms propagation delay times gnd gnd 3 v 1.5 v 1.5 v 1.5 v 1.5 v t w output enable low-level output high-level output 3 v ol gnd 3v 1.5 v 1.5 v 1.5 v 1.5 v oh ov gnd oh ol 1.5 v 1.5 v 1.5 v 1.5 v input in-phase output high-level input low-level input v v v v 1.5 v 3 v t s t h t plz t phz t pzl t pzh t pd t pd (1)
33 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1753 santa clara, ca 95054 fax: 408-492-8674 email: fifohelp@idt.com www.idt.com ordering information 4663 drw 29 blank pf pqf 12 15 20 l 72v3614 commercial (0 c to +70 c) thin quad flat pack (tqfp, pn120-1) plastic quad flat pack (pqfp, pq132-1) commercial low power 64 x 36 x 2 ? 3.3v s y ncbififo xxxxxxx idt device type xxx x x power speed package process/ temperature range clock cycle time (t clk ) speed in nanoseconds note: 1. industrial temperature range is available by special order. datasheet document history 07/10/2000 pg. 1. 05/27/2003 pg. 6.

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